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Honored Contributor
Honored Contributornewbie asks about "LATCH primitive ... is permanently disabled"
Folks, I have a DE1 (CycloneII starter board) to learn VHDL and Quartus. I developed and successfully tested my bit-shifting FIFO UART on the DE1. With this design functional, I'd like to move it ...
Altera_ForumHonored Contributor
Honored ContributorHello Craig,
I also expect that the code is synthesizable, otherwise you get an error. But there are some cases, particularly with asynchronous logic, that may be misunderstood by the synthesis tool. You can check the implementation in a simulation or interrogate the RTL and Technology Map netlist views. The latter will also reveal the implementation differences between logic families. Regards, Frank
