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Altera_Forum
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13 years ago

New bie on timing constraints

Hello Experts, I have been new in Altera & Quartus. I am trying to understand the need for constraints like 'set_clock_latency' , 'set_clock_uncertainity' in FPGA's. For me these constr...
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Altera_Forum
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13 years ago

Thank you all.

So in summary, there is no requirement to add 'clock_latency/uncertainity' for FPGA based designs since this should be taken care by default.

Do you all agree ?

Regards,

frk