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Altera_Forum
Honored Contributor
Honored ContributorNew bie on timing constraints
Hello Experts, I have been new in Altera & Quartus. I am trying to understand the need for constraints like 'set_clock_latency' , 'set_clock_uncertainity' in FPGA's. For me these constr...
Altera_ForumHonored Contributor
Honored ContributorYou are right about PLLs but the compiler wouldn't know your clock if it is external. Moreover the compiler wouldn't know the timing pattern required for io so you need to tell it. It also needs help to set false paths or multicycles(these may be automated in future!)
