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Honored Contributor
Honored ContributorNegative spykes on all internal signals in EP4CE15E22C7N
Hello. I use the EP4CE15E22C7N device. (E144 package). The only clock connected is 50MHz, 3.3V to one of the clk inputs. The VCCIO connected to clean 3.3VDC, the VCCINT and VCCPLL to clean 1.2...
Altera_ForumHonored Contributor
Honored ContributorThe spykes i see in SignalTap are 1 sample wide, so i assume that if there are phisical spiles, there are very narrow and maybe my oscilloscope with 200MHz bandwidth isn't enough to catch them.
Maybe ill implement a logic which detects spykes and producing an error output if there is one... Yes, i had verify that the oscillator is 50MHz, I also involved PLL in 1:1 configuration with same results. The "locked" signal was '1' (permanently), but i seen the same one-sample spykes on it also as on all other signals. If PLL looses its lock, it goes to "0" for much longer period, isn't it? I had created an internal signal which is constant '1' value and doesn't depend on anything, even not on reset. and i still see spykes on it... I must say that this issue looks very strange to me.... this is the 1'st time i use Cyclone IV device... In the past, with other Cyclone, Stratix and Aria devices i didn't got anything like it...
