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Altera_Forum
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14 years ago

Negative spykes on all internal signals in EP4CE15E22C7N

Hello. I use the EP4CE15E22C7N device. (E144 package). The only clock connected is 50MHz, 3.3V to one of the clk inputs. The VCCIO connected to clean 3.3VDC, the VCCINT and VCCPLL to clean 1.2...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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When i take to SignalTap a counter w/negative logic Sync Reset input and feed it with a constant '1' (created using the noprune attribute) i can see that when SignalTap shows negative spike, in some cases the counter resets, so it looks like the spike is real...

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Hi,

did you see a break down in your core voltage or I/O voltage, when the design is running ?

Kind regards

GPK