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Altera_Forum
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14 years ago

Negative spykes on all internal signals in EP4CE15E22C7N

Hello. I use the EP4CE15E22C7N device. (E144 package). The only clock connected is 50MHz, 3.3V to one of the clk inputs. The VCCIO connected to clean 3.3VDC, the VCCINT and VCCPLL to clean 1.2...
Altera_Forum's avatar
Altera_Forum
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14 years ago

As a simple test, if you reload the Signal Tap recording with the "Read Data" button, do the spikes appear in the same position? If not, it's rather a JTAG signal quality problem than a real spike.