Honored Contributor
Honored ContributorAfter spent a good week optimizing the location of output pins (to avoid SSO issues), by locating the global resources (clock and reset), it turn out to give a overall help in timing!
I was able to quickly use <assignment editor> to add a handful of nodes that fails timing, after define very specific submodule and constraint them to only 2-10 fanout, its brought the design down to 11 errors. Hope this is a good input for your document. As for incremental compile, a couple of issue I encounters are: 1. The TOP block cannot be set to empty, this appeared to be an tool issue that if any of the modules rely on PLL input/output, it won't get instantiated and the partition block will fail to route. As a result, I set TOP to "Source File", which still provide the flexibility to partition the remaining of the logic. 2. When setting the partitions to Post-Fit. The overall utilization rise from 80% to 97%. It definitely gave us an uneasy feeling picking the device, while it's obvious the FPGA has lots of unused block remaining looking at Chip Planner. So, this maybe another tool issue and I have end up setting all of the partitions to Post-Synthesis instead, mainly to get an accurate benchmark of all the compiles. With LogicLock I was able to obtain consistent timing result with sometimes a big step backward when moving the LogicLock areas around. All in all I am happy to dive into this subject and tweak the last bit of timing error out. Thanks for creating these intuitive documents!
