Honored Contributor
Honored ContributorThank you very much for the advice!
One additional factor is the design is high in utilization at between 79-84%, but moving to the next device did not address the timing issue to the group of troubled signal I tend to get. Most of the error are right in between the inter-modules (4 out of 14) where I partitioned them. I've tried the register re-timing, duplicate and do not remove duplicate registers and the result seem reasonable. When attempted to do a merge for the inter-modules the problem become too complex and I don't think I am making better decision than the tools since all modules are ultimately chained together, eventually no partition could sometimes yield to better result but I get nothing in control and only wish the pushing button solution works when more logic need to be added! Trying parent/child LogicLock region seem to help for certain timing error where datapath and placement were critical. For example: Region 1 and 7 in the screen shot specifically uses DSP multiplier/adder, by pack them really closely these are failing in the 60-100ps at 300 Mhz which are on/off the failing path list. From the document you provided, they can be set to Post-Fit once there's no timing error between parent/child. I end up using source file for all compile because the compile time is relatively the same, and by using post-fit the utilization is reported at 97% while we still see lots of empty spaces. Nevertheless it gave us an uncomfortable feeling toward picking the size of this FPGA...but low 80% maybe OK! I will give a try to max-fan-out for register feeding the long stages of adders and keep you posted. One other failing path I seem to have most trouble is the block ram output to a nearby location which tool claim a high number of delay, while physically it is already placed at the closest input/output... Should these be considered to fix using the register duplication technique? Thanks again! https://www.alteraforum.com/forum/attachment.php?attachmentid=6766
