Need Help to Verify Timing Constraints On Output Pins to External Device

Didn't even notice that. Yeah, a 200Mhz and 300Mhz clock would not be related.

In some instances it's clear from the clock frequencies that they just can't be related. But it's also design dependent. Let's say you bought IP that had two clocks that could be asynchronous, and you feed it with a 100Mhz and 50Mhz clock that are aligned, you could still cut timing between them because the design treats them that way.

In your case:

- Have the PLL output 25MHz too. Don't use the 25MHz before the PLL as that will be a different phase than if it goes through the PLL.

- Does your design have paths between 25MHz and 75MHz? If so, does it treat them as synchronous? They can be synchronous because they do have similar edges. By default you will have a 13.333ns setup relationship between the domains. But from a transfer perspective, you have 3 clocks of the 75MHz for every 1 clock of the 25MHz, so make sure it can handle this. If passing "data", it can be difficult. If passing control signals that are slow, then it might be fine.