Need Help to Verify Timing Constraints On Output Pins to External Device

Hi Ryan, Hi Everybody,

thanks alot for your answer. The guides written by you and your comments are helping me understand Timing issues.

In the document "TimeQuest User Guide" there is a very interesting example with the clock groups, page 12 "Quick tip for writing set_clock_groups constraint". I am not sure about some parts of the example.

1) The clock system_pll|..|clk[2] with 50 MHz is asynchronous to the pll outputs 125 MHz system_pll|..|clk[0] and system_pll|..|clk[1]. That's ok for me.

But why is the_adc_pll|..|clk[1] with 200 MHz and the_adc_pll|..|clk[1] with 300 MHz (in the example even 300.03 MHz and 3.333 ns) in the same clock group?

2) I have a pll with clock input 25 MHz. The clock outputs are

- 75 MHz (in the "Clocks Summary" shown as 75.0 MHz, 13.333 ns) and

- 150 MHz (150.02 MHz, 6.666 ns).

Are the 25 MHz, 75 MHz and 150 MHz clocks in the same clock group? Actually I think that they should be synchronous, because 25 Mhz x 3 = 75 MHz. But how can the periods of 40 ns and 13.333 ns be synchronous?

Thanks alot! With kind regards!