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I strongly believe it is possible for DDR to have slacks more than half period (UI) for either setup or hold and that is direct outcome of setting false paths between unrelated edges. You should not think of DDR clock as equivalent to SDR at double rate clock in which case it is not possible.
The DDR will have two registers to de-interleave data and so changes are ignored by one edge or the other.
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OK. I think this makes sense. I wasn't taking into account the topology of the DDR cell. So now I'm a bit more sure (or less unsure) that it's possible to have slacks greater than UI (but less than period). I will try to do my analysis/tests again having this in mind. I'll post the results.
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Regarding same edge Vs opposite edge latching, you are free to try either and see which one passes. Once you choose one case then your design must be aware of it. Remember a stream of Hdata => Ldata if sampled on same edge will retain the sequence and if you decide on opposite edge transfers then the sequence becomes Ldata => Hdata and as long as you interleave/deinterleave back correctly then it should work.
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I'm ok with this. The external device has a parity check that can be used to see if it's receving the data in the right way or not. If not, I can swap Ldata with Hdata to align it correctly.
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If you don't set false paths on irrelevant edges then slack must be less than UI and this is unrealistically too restrictive.
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Thanks!
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