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Honored Contributor
Honored Contributorneed help in correcting errors in fifo verilog
Can u help me debug errors in the fifo code? I am trying to find error but I have not suceeded in finding any. module newfifo(rst, clk, din, wr_in, //write_enable signal rd_in,...
Altera_ForumHonored Contributor
Honored Contributoryou will get one clock delay from address sampling point at least since sampling is at clock edge e.g. when address = 0 then it is read as zero at incoming clock edge and data0 becomes available at next clock edge.
With regards to x states this is trivial, you can just initilise your array mem but is not essential.
