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Altera_Forum
Honored Contributor
Honored Contributorneed help in correcting errors in fifo verilog
Can u help me debug errors in the fifo code? I am trying to find error but I have not suceeded in finding any. module newfifo(rst, clk, din, wr_in, //write_enable signal rd_in,...
Altera_ForumHonored Contributor
Honored Contributoroops!! i just understood the mistake now..thanks a lot!! but now,i realise that there are a few errors like immediately after my data_in is over, for a certain period of time although my rd_in is high, i don get dout immediately. its like there is an xxxxxxx state for one clock pulse before my dout starts. can u give me some tips on how to change so that i get my dout immediately after my din stops?
