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Honored Contributor
Honored Contributorneed help in correcting errors in fifo verilog
Can u help me debug errors in the fifo code? I am trying to find error but I have not suceeded in finding any. module newfifo(rst, clk, din, wr_in, //write_enable signal rd_in,...
Altera_ForumHonored Contributor
Honored ContributorYour code is active on low reset but your testbench raises reset so your design stays under reset. You need to release the reset by lowering it to '0'
