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Altera_Forum's avatar
Altera_Forum
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15 years ago

need help in correcting errors in fifo verilog

Can u help me debug errors in the fifo code? I am trying to find error but I have not suceeded in finding any. module newfifo(rst, clk, din, wr_in, //write_enable signal rd_in,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I am sorry, I have not understood. do i need to check reset in my program? (reset is an asynchronous active low signal in my case.) can u explain in a slightly detailed manner?