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Altera_Forum's avatar
Altera_Forum
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13 years ago

Multipreocessor , TSE and micro os II

Hi all,

I'm working in a multiprocessor system, it contains 3 processors to process some data and each processor store

the result in different shared on-chip memory (another processor get this data and display it)

now I added the tse core to get this data and send it through the internet in addition to be displayed in the lcd .

I connect m_read from sdgma_tx to the 2 different different shared memory the same for m_read sdgma_tx.

it's my first project and I don't know if it's correct what I did (the system compilation was successful),

or I have to copy all different data to the same location and the m_read and m_write should be connected to this single memory .

another question please, is about the usage of micro OS II in the network stack ,

the original systems work without operating system,

so I want to know if it's possible to use the micro os II

for the network stack and keep the other part as it is .

sorry for those basics questions.

many thanks in advance

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The easiest way is to dedicate only one of the processors to network traffic. Then you only need to connect the DMAs to the memory used by that processor, and if you need to share data with the other processors you can do this on the application level.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you Daixiwen you help me a lot .

    Since two months I am trying to deal with TSE and multiprocessor but I failed

    So I change the configuration as you recommended. You said that the easiest way,

    the other way is to change the TSE driver so we can handel multiprocessor ?

    Thank you again.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes you'll probably need to change a lot in order to use it with several processors. First you will need to protect access to the DMAs using a hardware semaphore, to be sure you'll never have two CPU trying to use a DMA at the same time. The other problem you will have is with packet reception. When you receive a packet, how do you know which CPU should handle it?

    In order to help more you should explain why you have several processors and what their roles are in your system.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi

    Thank you again!

    I think I did not explain well , here an image explaining briefly my architecture (what I want to do) and if possible of course!

    http://i46.tinypic.com/2e307ph.jpg

    For the time been the output is displayed on the LCD the data are from the different on-chip memory, so I want to add to TSE

    to get the data from all shared memory and send them.

    Another question please, is it possible to send the obtained data(even for one processor) directly to a distant server or a database through the internet,

    because it's my final goal and I want to avoid using an intermediate workstation

    Many thanks
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I see more clearly now. With this system you don't need a multiprocessor version of the TSE driver. The driver and the TCP/IP stack needs only to run on the "Master CPU", just as if it was a single processor system. You just need to have a synchronization mechanism between your processors so that they can warn "Master CPU" when new data is available, and the master CPU can read the data and send it.

    If you are using the ucOS II and the altera drivers, then the TSE SGDMA masters only need to be connected to the Master CPU's main memory, they don't need to be directly connected to the shared memories. As you use the TCP/IP stack, it is the stack that will read the data from the shared memories and recopy it to internal buffers used for the TSE.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If your 'shared memory' blocks are 'tightly coupled data memory' on the slave cpus (it probably makes sense to dedicate the second port to one of the masters), you do need to ensure they are set to return 'OLD_DATA' during concurrent read and write.

    For OLD_DATA to work they must use a single clock.

    Qsys has an explicit option for single clock - which works ok.

    SOPC builder will infer a single clock under some circumstances, but not if one of the masters is a Nios cpu (because it qualifies the clock). In this case if you tick 'OLD_DATA' the request is silently ignored.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you dsl for your comment !

    I'm using SOPC builder, my system is without OS, I'm planing to add microc/osII only for the use in the network stack

    and I'm not using 'tightly coupled data memory' I have only one master which is a niosII cpu , all others processors are for data processing only.

    is that Ok ?

    Thank you again
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    If your data processing cpu have a small code and private data, and it would be internal fpga memory, then there is no point also having instruction/data cache - it just uses up resource.

    I use 2 cpu, neither has any OS, one has under 4k bytes code, the other 8k (we actually increased the memory block because some diagniostics hit the limit). Together these support sixty four 64k hdlc data streams - one of the cpus only job is the hdlc tx/rx (including bit stuffing and crc generation), if the code were any bigger it wouldn't run fast enough!

    In my case the hdlc frame data is in SDRAM - accessed without any cache as single bytes (cache wouldn't help).