Honored ContributorI am looking at using a hw multiplier in a feedback control loop. Looking at the multipliers in CII and CIII parts, it looks like it is a single cycle multiply, 18x18 or 9x9. So the fastest I could read an external A/D, multiply, and present the result out on a bus would be conversion time + two system clocks. Does this sound correct or do the multipliers take more time?
Honored ContributorHi Tns1:
The Hardware multiply's are cycles can be setup as a unregistered, single cycle, 2 cycle or 3 cycle without using external LE's. So how you use them is up to use them is up to you, and the max clock frequency you run them at. For High frequency, (> 100 MHz) I suggest for 2 cycle multiply, for slower stuff, you can use a single cycle. PeteHonored ContributorI have 16bit multipiers running on 160 MHz with just a 2 clk mulitcycle in Cyclone II (speed 8).
Honored Contributori am very blurr about this one . Since i use the cyclone quartus II , when i need to create the multiplier, i just use the megafunction to create it . Is it okie when i did that?? and what happen if i use this program to the FPGA board??
