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Altera_Forum
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12 years ago

Multi IO voltage JTAG

My circuit is composed 4 Stratix4s per chain. And each FPGA has multiple IO voltage. (see attachment picture) Vccio of each FPGA's bank1A is connected to 2.5V. So we connected pull-up to 2....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi FvM,

Thank you for your reply.

It's lucky.

Anyway did you mean, even if other IO bank is connected different VCCIO, it is nothing to JTAG interface right ?

Boundary cells are supplied from each VCCIO, so different IO bank might cause the error when signal shift to next cell.

That's my concern.

I want to clarify my concept.

Thank you ~