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Honored Contributor
Honored ContributorMulti IO voltage JTAG
My circuit is composed 4 Stratix4s per chain. And each FPGA has multiple IO voltage. (see attachment picture) Vccio of each FPGA's bank1A is connected to 2.5V. So we connected pull-up to 2....
Altera_ForumHonored Contributor
Honored ContributorYour JTAG chain is apparently all-2.5V. Why should it need a level translator?
Extensive JTAG chains might have problems with crosstalk of fast on-board to JTAG signals, particularly TCK. In this case, buffers can be helpful sometimes.
