Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Modelsim test vector to verify DDC/DUC working?

Hi there, I'm looking for Modelsim version in verilog test vector to verify my DDC/DUC working good or not. By using signal generator as input and look at signalTap to see the result. But no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

first create some stimulus (using MATLAB, Octave, etc) and save it to a .txt file. then read the text file in your test bench and feed it into your system

you can see an example by creating a filter with FIR Compiler and taking a look at the generated test bench