Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

model a buffer in VHDL

Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dear turhank,

This model is for simulation. Is that means i need to write a<= b after 1ns; for register code? and no need to use buffer component.

Correct me if am wrong.Thank for response