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Altera_Forum's avatar
Altera_Forum
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14 years ago

model a buffer in VHDL

Hi, Im trying to model a buffer in VHDL but am unable to do so. I have signal A and B. I want the first signal A is loaded into a register after 2 seconds. Then, the signal B is generated ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

you also have error in first instantiation, it should have 3 ports not two ports