Mixed LVDS diff & single-ended signal I/O Bank

General rule with dealing placing LVDS different signals and single-ended signals on the I/O bank? OR just don't do it!

Cyclone IV, Ref AN592 Design Guide, pg 27; "The placement of single-ended I/O pins with respect to differential LVDS I/O pins is restricted. Follow the pin placement rules that specify the number of I/O pins that must separate single-ended outputs and LVDS I/O."

Anybody knows the amount of the bank pin separation to this? I be unable to find the pin placement rule related to this. I can understand why would need the separation from power or signal integrity issue. I need as many I/Os as I can get for the design.