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Altera_Forum
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14 years ago

Minimum pulse width violation

Hey guys, I'm using the timequest analyzer. I first setup the clock using the wizard. 120Mhz. I'm using Cyclone II, C6. After performing compilation and checkin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for the help ashishkaps. If the clock frequency is acceptable, then what could be causing this problem?

I can't avoid the latches. The altsyncram memory is synchronous. Every input to the module is latched with the clock. It seems that the error is occuring with that component.