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cjamcki's avatar
cjamcki
Icon for New Contributor rankNew Contributor
1 year ago

MAX10DD devices seem to not support ADC Blocks ?!?

we have a design targeting 10M50DDF256I7G. The device overview claims to support analog features as well as RSU, and some special flash access (not sure what that is but whatever). However, in Qsys...
Fpga Devkit
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
you can make a very simple test, instantiate the add IP as top level entity. As expectable, failing of adc IP synthesis results in design generation failure.

Error (12252): Adc_bad.modular_adc_0: The selected device part number 10M50DDF256C8G does not support ADC
=>

Error (12153): Can't elaborate top-level user hierarchy

(checked with Quartus Prime Std. 22.1)