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cjamcki's avatar
cjamcki
Icon for New Contributor rankNew Contributor
2 years ago

MAX10DD devices seem to not support ADC Blocks ?!?

we have a design targeting 10M50DDF256I7G. The device overview claims to support analog features as well as RSU, and some special flash access (not sure what that is but whatever). However, in Qsys...
Fpga Devkit
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


May I confirm with you, for the Max 10 DA device, the design can be compiled successfully with the IP? If yes, can you please share with me the design or else, the IP parameters setting such as the sequencer, etc?


Regards,

Aqid