Forum Discussion
New ContributorMAX10 using external PLL with soft-lvds gives always a warning: Warning (15064): PLL... jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Hi @SZand
Let me sum it up. There are 2 issues
1) warning on non-dedicated output clock
2) sdc constraint output paths
For (2), you might want to put on a new thread and refer to this thread so that my colleague could take detail look into your case.
For (1), Pll-c3(1:1): LVDS-clockpins which was supposedly your tx_outclock, should be connected to dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Example pin 32/33.
50/52 is not a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Thus the warning.
There isnt any sdc constraint that can dismiss the warning.
New ContributorHi JwChin,
thank you for your answer.
No, the the LVDS-Clock (as 1:1 clock from the pll) is connected to pins 50/52 (10M16SAE144).
The jitter problem seen on the display is solved (timing problem of the input latch not inside the SOFT-LVDS), but the above warning is still there. There are also other warnings from Timequest regarding not constraint output paths (all LVDSp/n pin paths).
I am interested in getting less as possible warnings. Probably there are settings in the sdc file that can be used to tell Quartus / Timequest that all is ok.
Best regards.
