Max10 power consumption with and without PLL

Hi, Kindly find the inline answers 1. What else (other than the PLLs) is VCCA supplying to have such current draw? >> It is the power to PLL and ADC block and have to connect to power supply even PLL and ADC are not in use reference page no: 15 https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-10/pcg-01018.pdf 2. When there is no PLL in the design whatsoever, why is VCCD_PLL still drawing 4.09 mA static power? >> As per the architecture of Max 10 FPGA the module will draw the current even PLL is not using and you cannot left this pin unconnected from power supply 3. Rather than just not using a PLL in the design, is there maybe a way to completely disable the FPGA's PLL feature in order to reduce the static power consumption? >> No, you have to provide the supply as per the recommendation from Max 10 Pin connection guidelines