Max input Voltage for single ended clock input (Stratix IV)

​Good morning

I have not heard back from you and wondered if you were able to provide an answer.The table I included in the original post was taken from the following document...

ttps://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-iv/stx4_siv54001.pdf

Table 1-17 (Single-Ended I/O Standards) on page 1-12.

If you are able to advise it would be much appreciated.

Best regards

Simon