MAX 7000 Help

Your Verilog syntax is wrong. And I guess you're misunderstanding how pin assignment is done.

what you want is something like

module testing_123(
output wire ctrl0
);
assign ctrl0 = 1'b0;
endmodule

Then you synthesize the design. It should work, and you should get some warnings about assigned pins.

You don't assign actual pins in the Verilog code though.

Then you go to the Pin Assignment Editor and you assign I/O signals of your top level entity to FPGA pins.

In this case, I guess you want to assign "ctrl0" to "PIN_10".