MAX 2 Shift Register delay problem

software : Quartus II Subscription Edition 9.1 sp2

use device : epm1270t144c5n (http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1333-nd)

use kit : Developing board

pc os : Windows 7 32bit

I am developing 13ea SPI(Serial parallel interface) communication in the board.

In order to develope many spi module, I decided to use the CPLD.

First, It is implemented shift register Mega function in Quartus 2 to SPI TX, RX.

Physical layer is using optic fiber to rapidly communication.

In order to check communication status, TX ports(chip select, clock, data) is connected to RX ports.

I succeeded in the experiment 1:1 SPI communiation.

But this block is increased in number, the problem began to occur.

To implement 13 SPIs, it was copy/paste these blocks(SPI TX/RX modules), But shift register did not work well. 4 works fine so far. But, from 5 works(copy/paste) is not good. shift registers had a large delay acitvity. CPLD is less than 50% of the utilization.