MAX 10 weird behaviour

It will be the routing inside the FPGA. The circuit will likely be the same.

When the design is compiled, the fitter uses a seed to place all the elements. This seed is dependent on your code and the project seed settings. Any change in the code changes the fit seed and hence where everything gets place.

Timing specs help guide the fitting by giving limits on how far the routing can go. Without the timing specs, you let the fitter run wild where some builds work and some don't.