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New ContributorMax 10 Pin Compatibility
Hi FPGA,
As long as they fall under the same package it shouldn't be a problem.
You can refer to the Migration Capability Across Intel MAX 10 Devices on page 8 in the following document:
Intel® MAX® 10 FPGA Device Overview
Regards,
Fakhrul
Super ContributorHello,
to be sure not to overlook any necessary connection in migration compatible devices, I'd proceed as follows
- select all intended migration devices in your Quartus design
- place a top level entity with all port signals and signal direction
- optionally add basic functionality for dedicated signals (PLLs connecting to clock in- and outputs, SERDES IP)
- assign locations and IO-standards for all signals
- compile the design
- review the required connection in generate .pin file. You particulary find all pins needing connection to GND or supply voltage for migration devices
Regards
Frank
FakhrulA_alteraRegular Contributor
Hi FvM,
As long as there's no error nor significant warning during the compilation process, plus with all your mentioned procedures above, it should be no issue.
Regards,
Fakhrul
