Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

MAX 10 LVDS and DDR

I haven't used LVDS before, and I want to interface to an 12-bit 125-MSPS ADC running 6-bit LVDS with DDR. Does the MAX 10 LVDS interface support this? If not, can I still use the MAX 10 LVDS interfa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

You don't need a PLL as the output clock DCO is centre-aligned to the output data, OUTA and OUTB, and the frame signal FR.

For word alignment: feed the FR signal into a DDR-In like the data and use the 01 transition (or the 10 transition) as the word-alignment indicator.

The other questions become clear when you study the Altera GPIO-Lite core in the max 10 general purpose i/o user guide