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Altera_Forum
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10 years ago

Max 10 FPGA

Hi, I am working on the MAX 10 FPGA board and I found that in the errata document it mentions: if your existing design por scheme is configured to use either fast por delay or slow por de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi Such

Have a look to this document https://www.altera.com/en_us/pdfs/literature/an/an730.pdf (see page 22 and 23).

The power on reset scheme can be set in convert programming file window by setting the mode to internal configuration and open Options/Boot info window.

I hope this helps. With best regards

Chris