--- Quote Start ---
Hi SStrel, tank a lot for assistance, that document was the first I found by googling around, at this moment I am not able to use this controller due it refuse reduce to 16 bit bus, I try more later.
About my code why
SRAM_Data <= avalon_slave_writedata when avalon_slave_write='1' else
(others => 'Z');
refuse to input/output data?
I am using similar code to read write an external bus (unrelated to SRAM) and it work fine, on RAM forever read 0 and seems not writing data to.
Next week I can collect some spare time and I test it Thorougly again to try isolate the problem from design. Using internal FPGA RAM work(final board with 10M50SC), using external DRAM (test board) it work, SRAM controller seems faulty. Again I cannot use nor NIOS nor JTAG debugger, when inserted on design refuse to compile with an error relative to Config flash, no way at this moment to inspect from internal bus, I arrange some test from external Logic Analyzer pod.
Best regards
Roberto
--- Quote End ---
Again thank for hints and moral support too, sometimes things behave differently than HDL seems be...
About this problem where where found how trouble come from.
Component generated from QSYS fabric, on TOP were redirected to local signals before pin, all work fine with input or output pin leaving space to test them and sample with an external connector not for tristate.
To test Input and output from tristate pin, tristate driver need to be replicated at TOP then sample in and out not from pin but from readdata and writedata. If read from INOUT it doesn't work at all:
- INOUT pins are no more connected the right way
- it generate bad code stuck to something not sure ('0' '1' or data)
- tristate function is lost to INOUT pins.
Removed this threat, then all core behave same way, my core, university core, also tristate controller; ( I solved about parameters reading another tons of docs). Every controller now read a strange "400A" pattern all across the RAM and also everywhere there is nothing on Avalon.
This I fear need a huge hardware debug and connection of LA to external bus, Actually I don't own a dev board with SRAM on it so I plan build an adapter to fit on some dev kit 40 pin connector and study what happen from there. I own micro grabber for LA bought long time ago, they perfect fit on .5mm but my eyes are no more the same.
The best way for next chip can be to have some internal SRam and or SDRam to avoid external fit with all these troubles and reducing pin count too.
Best regards
Roberto
Honored Contributor
