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Altera_Forum
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8 years ago

MAX 10: a clock for SPI

Is using an external clock without a clock buffer causing any problem? I'm implementing SPI slave. An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Be careful, your design is not fully synchronous so it complicates the timing constraints.

You should not have in_CSn in your sensitivity list to be fully synchronous with the sclk signal, and in your case, you probably want to be synchronous with sclk.

--- Quote Start ---

always @(negedge sclk or posedge in_CSn)

if (in_CSn) Cnt <= 3'd7;

else if (Cnt == 3'd0) Cnt <= 3'd0;

else Cnt <= Cnt - 1'b1;

--- Quote End ---