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Altera_Forum
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8 years ago

MAX 10: a clock for SPI

Is using an external clock without a clock buffer causing any problem? I'm implementing SPI slave. An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA...
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Altera_Forum
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8 years ago

Thanks Alex for our reply!

- How have you constrained your design?

Not yet, cause I thought actual this SPI clock (sclk) is not that fast as less than 50 Mhz.

Please give me some hints. I recently moved from Xilinx to Altera.

I'm going to look at tutorial adding constraint file, but I'll be happy if you give me some tips making less mistakes.

Regards,