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Honored Contributor
Honored ContributorManaging multiple clock domains in verilog
Hopefully a pretty basic question with a simple solution (ha ha ha) I've got a project with two major sub blocks. The first block includes a NIOS II processor and lots of verilog glue logic to...
Altera_ForumHonored Contributor
Honored ContributorRysc of course is correct. Because all of your clocks come from a single PLL, the global "Cut paths between unrelated clock domains" setting does nothing for you. This is because the clocks are in fact related by some combination of multipliers and dividers and they are all derived from the same base clock. You must therefore make individual cuts between the clock domains.
