Managing multiple clock domains in verilog

You can. Just do a cut timing between the clocks. I look at the timing report with the failures, and literally cut and paste from the From/To Clock columns into the Assignment Editor and just make Cut = On. That way I don't do it incorrectly. Note that you need to do both directions, from OSC_53 to OSC_68 and from OSC_68 to OSC_53. With three clocks, that'll be 6 different CUT combinations.

(And good job designing for the asynchronous clocks. That's the hard part.) When you get a chance, take your design, launch TimeQuest, and run the QSF to SDC conversion and then just run TimeQuest with that newly created SDC. Note that you haven't committed or anything, as Classic is still your timing analyzer for the whole flow, but you can use it as back end tool to just kick the tires. You'll hate it at first, but you'll quickly love it.