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Altera_Forum
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18 years ago

Managing multiple clock domains in verilog

Hopefully a pretty basic question with a simple solution (ha ha ha) I've got a project with two major sub blocks. The first block includes a NIOS II processor and lots of verilog glue logic to...
Altera_Forum's avatar
Altera_Forum
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18 years ago

jakob -

Thanks for the quick reply ..

1) Yes I'm using the Classic Timing Analyzer

2) Yes, all the clocks are on the same PLL.

Until such time as I invest the effort to learn the TimeQuest analyzer any ideas about how to care for my issues? Can't I have 3 different outputs from a given PLL and NOT have have them related for Timing Analysis?