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Altera_Forum's avatar
Altera_Forum
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18 years ago

LVDS test with Boundary Scan

I am having an ADC with LVDS outputs , the lvds outputs are conected to a Stratix III.

I want to test the Stratix LVDS inputs with Boundary scan .My plan was to use a DAC (or R2R) connecting to the ADC .

It's no problem to create patterns for the DAC, but I am having some problems (i think) to detect de LVDS levels on the fpga site.

Using MorphIO ? ( I do not have experience with this)

Or configure the Stratix with a TAP controller and LVDS Rx to a "single normal" level / boundary scan cell ?

Does anyone has an idea ?

Thanks , Hans

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Stratix III does not support LVDS boundary scan. Only the P pin can accept the signal while the N pin is ignored. You can use BSDLCustomizer from Altera to modify the BSDL file to test for LVDS pins.