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Honored Contributor
Honored ContributorLVDS recieve(ep2s)
Hello! In my Project,I have 8 separate data channels using LVDS. The Data clock is up to 300MHz. the data is clocked out of the ADC and must be captured on the rising and falling edges of the data...
Altera_ForumHonored Contributor
Honored ContributorYou should use dedicated LVDS RX differential pairs, they have internal termination resistor and can achieve up to 1 GBps data rate with Stratix II I4 speed grade. The selection of suitable input pins is most easy in Quartus Pin Planner tool, it also enforces observance of other pin placement rules.
Stratix II has dedicated SERDES circuitry, the bitclock is generated internally by a PLL, you have to connect only ADC frame clock as a reference. You should also enable the option to send test patterns from the ADC, this allows automatic bit phase and frame alignment in your design during initialization.
