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Altera_Forum
Honored Contributor
Honored ContributorLVDS Receiver PLL
I am using using a Stratix II with Quartus 7.1 SP1. When using an LVDS receiver the fitter automatically assigns the input clock as LVDS as well. How would I clock the LVDS receiver using singl...
Altera_ForumHonored Contributor
Honored ContributorI have heard of this problem before and I believe there is a software patch available to allow a different IO standard for the LVDS PLL reference clock. I believe I've read somewhere the LVDS restricition is to achieve the best possible jitter tolerance to maximize timing margin at the highest rates.
I would recommend filing a service request with Altera's mySupport for access to the software patch. Regards, Chris Edit: I see Frank found a work around using the clkctrl... try that first ;)
