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Altera_Forum
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14 years ago

LVDS cycloneII to 10 bit counter

In cycloneII manual i read the max freq input LVDS pin is >800MHz. IF i have a 750 MHZ signal as input, and i send it to LVDS input (cycloneII), can i divide this freq with a 10-bits counter? ...
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Altera_Forum
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14 years ago

Hi Thieulam,

So the design requirement is really, measure the frequency or number of transitions on a signal in 0.5us. The signal frequency is 5.4GHz/8 = 675MHz to 5.9Ghz/8 = 738MHz.

This signal is essentially asynchronous relative to the FPGA clock domain.

Given that the signal is pulsed, you cannot use it to lock a PLL.

The pulse frequency is too high for the clock reference pins on an FPGA. Can you divide it one more time? Eg., use an external divide-by-16?

If you can reduce the frequency to the point where you can get the signal onto an FPGA clock pin (or I/O pin if the fmax of the pin is not violated), then internally you can create the following logic;

You need an accurate FPGA clock; this will be used to generate a reference gate signal. The gate signal needs to assert when the pulse starts, and stay asserted for the length of the pulse. For example, lets say an incoming pulse 'triggers' your gate signal, which is then enabled for 0.4us, during which time the incoming pulse clocks a counter. The count at the end of the pulse then determines the incoming frequency.

The tricky part is generating the gate pulse. I'd try something like the following; use a register that gets 'set' by an incoming pulse clock edge, i.e., this would get set when the first pulse clock edge arrives. Synchronize that to the FPGA clock domain, and use that to enable the generation of a 0.4us enable pulse from the accurate FPGA clock domain. Then use the pulse clock edges to synchronize the 0.4us pulse in the pulse clock domain. Use the synchronized signal to enable the pulse clock edge counter. At the end of the 0.4us count, generate a handshake back to the FPGA clock domain indicating that the counter count is valid and stable. Read the count in the FPGA clock domain, and you can then determine the pulse frequency. Clear the register that was 'set' by the initial pulse edge (this will need to be an asynchronous reset, since there is no clock in the other domain when there is no pulse).

Cheers,

Dave