LVDS cycloneII to 10 bit counter

Hi Thieulam,

If it really is a 750MHz clock signal that you want to slow down, then it is too fast for the FPGA I/O pins. You would need an external divider. Micrel make plenty of high-speed dividers.

Check the Cyclone II data sheet for the PLL specifications. You could divide your clock down to the PLL reference fmax, and then route the divided signal to a PLL reference pin. Alternatively, divide the clock down to below the I/O pin maximum frequency.

What do you hope to do with this signal once you get it into the FPGA?

Cheers,

Dave