LVDS cycloneII to 10 bit counter

Hi Thieulam,

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In cycloneII manual i read the max freq input LVDS pin is >800MHz.

IF i have a 750 MHZ signal as input, and i send it to LVDS input (cycloneII), can i divide this freq with a 10-bits counter?

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Division is the term usually applied to reducing the frequency of an external clock. I think that what you are really asking is about serial-to-parallel conversion of a data stream. The LVDS SERDES receiver blocks (ALTLVDS) can perform serial-to-parallel conversion, and I believe 1:10 is a supported mode. In general, the ALTLVDS component needs a data lane (or lanes) and a reference clock. In your case, you would have a 75MHz reference clock, a 750Mbps data lane, and 1:10 serial-to-parallel conversion mode.

You should use Quartus to configure an ALTLVDS component for your target device. Quartus will check that your data rates are compatible with the FPGA speed grade you have selected for your project.

If the Cyclone II part does not work, the Stratix II can support over 1Gbps data rates, as do newer Stratix series devices. The newer Cyclone series devices are probably faster too.

Cheers,

Dave