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Hi,
I have used a couple of dual clock fifo's in my design and have experienced problems with reading data from them. It seems that I have to flush two null words out of the fifo's after a reset, before getting the real data. I have looked at the writing and reading on a logic analyzer and there is no evidence that those two words were written to the fifo by my design. The dual clock nature was necessary for the circuit, because the design requires simultaneous reading and writing to the fifo. The clocks are asynchronous. The write clock is a 4MHz clock, whereas the read clock is the rdreq signal delayed by one 16MHz clock cycle. The asynchronous rdclk is necessary because it is not possible to use a standard clock. The fifo is only read when it is greater than 1/8 full, so it is not a read empty problem. Anyone experienced this problem and have a solution ?
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lpm fifos including dual clock are mature and well known to be bug-free provided they pass timing.
your write clock is 4MHz (on every clock).
your rd clock is not clear. what do you mean by 16MHz delay. what do you connect to read clock and what do you connect to rd request.
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