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There is no "time". If you go without a clock then the propgation delay will be affected by PVT (process, voltage, temperature) and routing meaning every time you compile it the prop delay will be different. And to top it all off, you have no idea how long it takes before it would be stable as there is no way to measure it.
With a clock, you can measure all these things and you know the "turnaround" time. And to top things off, the higher the pipeline delay, the faster the clock speed you can achieve.
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My system clock is 3MHz, that means to have a result in one system clock cycle can i use I higher clk (for example 10Mhz) for the divider with pipeline?
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