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4 wires: 80MHz clock, 3x 80Msps datastreams, datastream1 = 4MSBs of channelA, then 4MSBs of channelB. datastream2 = 4MediumSBs of channelA, then 4MediumSBs of channelB. datastream3 = 4LSBs of channelA, then 4LSBs of channelB, having clocked out 8bits on each datastream the whole thing repeats. There is no 'latch' all timing is dead reckoned off a starting pattern. (yuk)
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Ok, this sounds straightforward enough. The implementation will require a finite state machine (FSM); it will synchronize to the start pattern and then demultiplex data using counters.
If all three data streams use the same clock, then one FSM can be used. If not, then separate FSMs are required.
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1.8V CMOS. (I believe.. silicon is still in development but nealy done)
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This is no problem for either a CPLD or FPGA.
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The problem is the tester clock that the data has to be aligned too is not good enough to drive the RF, so we are forced to have two asynchronous clocks, they are almost phase locked, so even with thousands of samples we
shouldn't get even one clock cycle drift. Trouble is "shouldn't" isn't "doesn't" and we can't afford to assume we won't get a problem... not if it risks bakcing up 10s of thousands of product chips.
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What do you mean by almost phase-locked? If the tester clock is phase-locked, but just has excessive jitter, then the system is still synchronous.
The key parameters in your selection between a CPLD vs an FPGA are;
* CPLDs do not have RAM blocks, so implementing FIFOs is expensive (uses lots of logic cells).
* FPGAs have more flexible clocking options and include PLLs.
I'd recommend starting by looking at the Cyclone IV series of FPGAs. Just select the biggest in a TQFP, and make sure you connect the ground pad when you create custom board.
80Msps is not too fast. I think you could do some prototyping with a Terasic DE0-nano pretty effectively (they're $80).
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The tester needs to be 'bus master' in whatever interface we have between the CPLD/FPGA and the tester. I'm envisioning a 12bit wide databus plus a few control lines, running at 20Msps.
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What does the "tester" need to communicate to the FPGA? Is it the tester that needs to communicate, or a control PC? If its a control PC, then its pretty easy to interface an FTDI FT232H USB-to-FIFO device and achieve 40MB/s data rates. The USB interface programming is as simply as using a COM port (or /dev/ttyUSB0 if you're a Linux guy).
Cheers,
Dave
Honored Contributor
